Ticket #2299: log.txt

File log.txt, 8.2 KB (added by Henning Kiel, 12 years ago)

omc output

Line 
1true
2record SimulationResult
3 resultFile = "",
4 simulationOptions = "startTime = 0.0, stopTime = 400.0, numberOfIntervals = 500, tolerance = 0.000001, method = 'dassl', fileNamePrefix = 'Modelica.Electrical.Digital.Examples.RAM', options = '', outputFormat = 'mat', variableFilter = '.*', measureTime = false, cflags = '', simflags = ''",
5 messages = "Simulation failed for model: Modelica.Electrical.Digital.Examples.RAM
6Error: Internal error BackendDAECreate.lowerAlgorithm failed for algorithm
7 if initial() then
8 (dLATRAM.mem, _, _) := Modelica.Electrical.Digital.Memories.DLATRAM.getMemory(dLATRAM.fileName, dLATRAM.n_addr, dLATRAM.n_data);
9 end if;
10 if dLATRAM.WE == Modelica.Electrical.Digital.Interfaces.Logic.'1' or dLATRAM.WE == Modelica.Electrical.Digital.Interfaces.Logic.'H' then
11 dLATRAM.int_addr := Modelica.Electrical.Digital.Memories.DLATRAM.address(dLATRAM.n_addr, {dLATRAM.addr[1], dLATRAM.addr[2]});
12 if dLATRAM.int_addr > 0 then
13 for i in 1:dLATRAM.n_data loop
14 dLATRAM.mem_word[i] := {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'X'}[dLATRAM.dataIn[i]];
15 end for;
16 dLATRAM.mem[dLATRAM.int_addr,1:dLATRAM.n_data] := {dLATRAM.mem_word[1], dLATRAM.mem_word[2]};
17 end if;
18 elseif dLATRAM.WE == Modelica.Electrical.Digital.Interfaces.Logic.'X' or dLATRAM.WE == Modelica.Electrical.Digital.Interfaces.Logic.'W' or dLATRAM.WE == Modelica.Electrical.Digital.Interfaces.Logic.'Z' or dLATRAM.WE == Modelica.Electrical.Digital.Interfaces.Logic.'U' or dLATRAM.WE == Modelica.Electrical.Digital.Interfaces.Logic.'-' then
19 dLATRAM.int_addr := Modelica.Electrical.Digital.Memories.DLATRAM.address(dLATRAM.n_addr, {dLATRAM.addr[1], dLATRAM.addr[2]});
20 if dLATRAM.int_addr > 0 then
21 dLATRAM.mem_word := {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X'};
22 dLATRAM.mem[dLATRAM.int_addr,1:dLATRAM.n_data] := {dLATRAM.mem_word[1], dLATRAM.mem_word[2]};
23 end if;
24 end if;
25 if dLATRAM.RE == Modelica.Electrical.Digital.Interfaces.Logic.'0' or dLATRAM.RE == Modelica.Electrical.Digital.Interfaces.Logic.'L' then
26 dLATRAM.nextstate := {Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'Z'};
27 elseif dLATRAM.RE == Modelica.Electrical.Digital.Interfaces.Logic.'1' or dLATRAM.RE == Modelica.Electrical.Digital.Interfaces.Logic.'H' then
28 dLATRAM.int_addr := Modelica.Electrical.Digital.Memories.DLATRAM.address(dLATRAM.n_addr, {dLATRAM.addr[1], dLATRAM.addr[2]});
29 if dLATRAM.int_addr > 0 then
30 dLATRAM.mem_word := dLATRAM.mem[dLATRAM.int_addr,1:dLATRAM.n_data];
31 for i in 1:dLATRAM.n_data loop
32 dLATRAM.nextstate[i] := {{Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U', Modelica.Electrical.Digital.Interfaces.Logic.'U'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L'}, {Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}, {Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'L', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'0', Modelica.Electrical.Digital.Interfaces.Logic.'L'}, {Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'1', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'Z', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'H', Modelica.Electrical.Digital.Interfaces.Logic.'1'}, {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W', Modelica.Electrical.Digital.Interfaces.Logic.'W'}}[dLATRAM.mem_word[i], dLATRAM.strength];
33 end for;
34 else
35 dLATRAM.nextstate := {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X'};
36 end if;
37 else
38 dLATRAM.nextstate := {Modelica.Electrical.Digital.Interfaces.Logic.'X', Modelica.Electrical.Digital.Interfaces.Logic.'X'};
39 end if;
40 dLATRAM.yy := {dLATRAM.nextstate[1], dLATRAM.nextstate[2]};
41
42Error: Internal error SimCode: The model Modelica.Electrical.Digital.Examples.RAM could not be translated
43",
44 timeFrontend = 0.0,
45 timeBackend = 0.0,
46 timeSimCode = 0.0,
47 timeTemplates = 0.0,
48 timeCompile = 0.0,
49 timeSimulation = 0.0,
50 timeTotal = 0.0
51end SimulationResult;