Changes between Initial Version and Version 2 of Ticket #4840


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Timestamp:
2018-07-04T05:57:28Z (7 years ago)
Author:
massimo ceraolo
Comment:

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  • Ticket #4840 – Description

    initial v2  
    11Consider the enclosed model BugSources. the source voltages are correct (plot1.png).
    2 Let us not set phase of sineVoltage component to {0,120,240} It should still create three sines equally spaced in time. However this happens not to be true (plot2.png).
    3 Since the circuit is very simple, as used only MSL component, I think this issue is severe.
     2Let us now set phase of sineVoltage component to {0,120,240} It should still create three sines equally spaced in time. However this happens not to be true (plot2.png).
     3Since the circuit is very simple, and uses only MSL components, I think this issue is severe.