Modelica_Synchronous.Examples.SimpleControlledDrive.ClockedWith_AD_DA_Effects

[Volker Waurich]

Hi,

In the stated model, there are 2 clockPartitions. One subclock has a shift of -1/5.

1) Is it valid to have a negative clock shift?

2) The small partition (3 vars) including hold1.compDelay.y is assigned to the subclock with shift 0.
I think this partition has to be assigned to the sub clock with the shift of 1/5.

Do you mind having a look on that?

[Bernhard Thiele]

Hm, I also would have expected that the small partition is delayed with a shift of 1/5 and the large partition starts without delay at the same time as the base clock. Instead, it shows the small partition to start without shift, while the large partition starts 1/5 before.

The plots show the expected (positive) delay, but the mapping of the sub-clocks seems weird.

It is possible to have negative clock shifts using the backSample operator. However, only a variable running on clock that previously has been (positively) shifted can be shifted back. Particularly, a clock cannot start before its base clock started, but the clock analysis output dump suggests that the large partition start before its base clock. Maybe we are just misinterpreting the output?

[Volker Waurich]

Thanks for investigating. The partition-subclock-mapping seems to be inverted and at least for the cpp-runtime, a shift of -1/5 causes a backsampling even before the base clock ticks.
If I revert the subclock order and set the shift to +1/5, I get the same as in Dymola (with deactivated noise of course).

Would you try to fix this? Might be faster. Otherwise I have to check clockPartitioning, although I am pretty unfamiliar with this module.

[Volker Waurich]

The new subclockpartitioning fixes this problem. I will close the ticket.